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RM5261TM Microprocessor with 64-Bit System Bus Data Sheet Released
RM5261
RM5261TM Microprocessor with 64-Bit System Bus
Data Sheet
Proprietary and Confidential
Issue 1, March 2001
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use Document ID: PMC-2002241, Issue 1
RM5261TM Microprocessor with 64-Bit System Bus Data Sheet Released
Legal Information
Copyright
(c) 2001 PMC-Sierra, Inc. The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers' internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc. PMC-2002241 (R1)
Disclaimer
None of the information contained in this document constitutes an express or implied warranty by PMCSierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage.
Trademarks
RM5261 is a trademark of PMC-Sierra, Inc.
Contacting PMC-Sierra
PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com
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Revision History
Issue No.
1
Issue Date
March 2001
ECN Number
3828
Originator
T. Chapman
Details of Change
Applied PMC-Sierra template to existing MPD (QED) FrameMaker document. Revised Features list, Sections 3.14, 3.19, 3.21, 3.22, 3.23, 3.26, 3.27, 3.30, 3.32, 5, 6, 7, 9.3, 9.4, and packaging diagram information.
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Document Conventions
The following conventions are used in this datasheet: *All signal, pin, and bus names described in the text, such as ExtRqst*, are in boldface typeface. *All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold typeface. *All instruction names, such as MFHI, are in san serif typeface.
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Table of Contents
Legal Information ...........................................................................................................................2 Revision History .............................................................................................................................3 Document Conventions .................................................................................................................4 Table of Contents ..........................................................................................................................5 List of Figures ................................................................................................................................7 List of Tables .................................................................................................................................8 1 2 3 Features ..................................................................................................................................9 Block Diagram .......................................................................................................................10 Hardware Overview ...............................................................................................................11 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Superscalar Dispatch ...................................................................................................11 CPU Registers .............................................................................................................11 Integer Unit ..................................................................................................................11 Pipeline ........................................................................................................................12 Register File .................................................................................................................12 ALU ..............................................................................................................................12 Integer Multiply/Divide ..................................................................................................13 Floating-Point Co-Processor ........................................................................................13 Floating-Point Unit .......................................................................................................13
3.10 Floating-Point General Register File ............................................................................15 3.11 System Control Co-processor (CP0) ............................................................................15 3.12 System Control Co-Processor Registers .....................................................................15 3.13 Virtual to Physical Address Mapping ............................................................................16 3.14 Joint TLB ......................................................................................................................17 3.15 Instruction TLB .............................................................................................................18 3.16 Data TLB ......................................................................................................................18 3.17 Cache Memory .............................................................................................................18 3.18 Instruction Cache .........................................................................................................19 3.19 Data Cache ..................................................................................................................19 3.20 Write buffer ..................................................................................................................21 3.21 System Interface ..........................................................................................................21 3.22 System Address/Data Bus ...........................................................................................21 3.23 System Command Bus ................................................................................................21 3.24 Handshake Signals ......................................................................................................22 3.25 Non-overlapping System Interface ...............................................................................22 3.26 Enhanced Write Modes ................................................................................................23 3.27 External Requests ........................................................................................................24 3.28 Interrupt Handling ........................................................................................................24 3.29 Standby Mode ..............................................................................................................24 3.30 JTAG Interface .............................................................................................................24
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3.31 Boot-Time Options .......................................................................................................24 3.32 Boot-Time Modes .........................................................................................................25 4 5 6 7 8 9 Pin Descriptions ....................................................................................................................26 Absolute Maximum Ratings ..................................................................................................29 Recommended Operating conditions ....................................................................................30 DC Electrical Characteristics .................................................................................................31 Power Consumption ..............................................................................................................32 AC Electrical Characteristics .................................................................................................33 9.1 9.2 9.3 9.4 Capacitive Load Deration .............................................................................................33 Clock Parameters ........................................................................................................33 System Interface Parameters .......................................................................................34 Boot-Time Interface Parameters ..................................................................................34
10 Timing Diagrams ...................................................................................................................35 10.1 System Interface Timing ..............................................................................................35 11 Packaging Information ..........................................................................................................36 12 RM5261 208-pin PQFP Package Pinout ...............................................................................38 13 Ordering Information .............................................................................................................40
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List of Figures
Figure 1 Block Diagram .............................................................................................................10 Figure 2 CPU Registers .............................................................................................................11 Figure 3 Pipeline ........................................................................................................................12 Figure 4 CP0 Registers .............................................................................................................16 Figure 5 Kernel Mode Virtual Addressing (32-bit) .....................................................................17 Figure 6 Typical Embedded System Block Diagram .................................................................21 Figure 7 Processor Block Read .................................................................................................23 Figure 8 Processor Block Write .................................................................................................23 Figure 9 Clock Timing ................................................................................................................35 Figure 10 Input Timing ...............................................................................................................35 Figure 11 Output Timing ............................................................................................................35
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List of Tables
Table 1 Integer Multiply/Divide Operations ................................................................................13 Table 2 Floating-Point Instruction Cycles ..................................................................................14 Table 3 Cache Attributes ...........................................................................................................20 Table 4 Boot-Time Mode Bit Stream .........................................................................................25 Table 5 System Interface ...........................................................................................................26 Table 6 Clock/Control Interface .................................................................................................27 Table 7 Interrupt Interface .........................................................................................................27 Table 8 JTAG Interface .............................................................................................................27 Table 9 Initialization Interface ....................................................................................................28 Table 10 Power Supply .............................................................................................................28 Table 11 DC Electrical Characteristics ......................................................................................31
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1
Features
* Dual Issue superscalar microprocessor * 200, 250, 266 MHz operating frequencies * 320 Dhrystone 2.1 MIPS High-performance system interface * 64-bit multiplexed system address/data bus for optimum price/performance * High-performance write protocols maximize uncached write bandwidth * Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9 * IEEE 1149.1 JTAG boundary scan Integrated on-chip caches * 32KB instruction and 32KB data -- 2 way set associative * Virtually indexed, physically tagged * Write-back and write-through on a per page basis * Pipeline restart on first doubleword for data cache misses Integrated memory management unit * Fully associative joint TLB (shared by I and D translations) * 48 dual entries map 96 pages * Variable page size (4 KB to 16 MB in 4x increments) High-performance floating-point unit: up to 530 MFLOPS * Single cycle repeat rate for common single-precision operations and some double-precision operations * Two cycle repeat rate for double-precision multiply and double precision combined multiply-add operations * Single cycle repeat rate for single-precision combined multiply-add operation MIPS IV instruction set * Floating point multiply-add instruction increases performance in signal processing and graphics applications * Conditional moves to reduce branch frequency * Index address modes (register + register) Embedded application enhancements * Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply instruction * I and D cache locking by set * Optional dedicated exception vector for interrupts Fully static 0.25 micron CMOS design with power down logic * Standby reduced power mode with WAIT instruction * 2.5 V core with 3.3 V IOs 208-pin PQFP package
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2
Block Diagram
Figure 1 Block Diagram
DTag DTLB ITag ITLB Primary Instruction Cache 2-way Set Associative
A/D Bus Pad Bus
Primary Data Cache 2-way Set Associative
Store Buffer Write Buffer Read Buffer
Pad Buffer Address Buffer
Instruction Dispatch Unit FP Instruction Register
FP Bus Integer Bus
Integer Instruction Register
D Bus
Floating-Point Control
Floating-Point Load/Align Floating-Point Register File Packer/Unpacker
Joint TLB
DVA
Load Aligner
Integer Control
Coprocessor 0 System/Memory Control PC Incrementer
FA Bus
Integer Register File Integer Address/Adder
IVA
Shifter/Store Aligner Logic Unit
Floating-Point MultAdd, Add, Sub, Cvt, Div, Sqrt
Branch PC Adder ITLB Virtual Program Counter DTLB Virtual PLL/Clocks Int Mult, Div, Madd
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3
Hardware Overview
The RM5261 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the RM5261 are briefly described below.
3.1
Superscalar Dispatch
The RM5261 has an asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. Integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high-throughput fully pipelined floating-point execution unit, the superscalar capability of the RM5261 provides unparalleled price/performance in computationally intensive embedded applications.
3.2
CPU Registers
The RM5261 CPU has a simple user-visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. Figure 2 shows the user visible state.
Figure 2 CPU Registers General Purpose Registers
63 0 r1 r2 * * * * r29 r30 r31 0
Multiply/Divide Registers
63 HI 63 LO 0 0
Program Counter
63 PC 0
3.3
Integer Unit
Like the RM5260, the RM5261 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the RM5261 includes three implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in a later section, these instructions are integer multiply-accumulate and 3-operand integer multiply. The RM5261 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous
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multiply/divide unit. Additional register resources include: the HI/LO result registers for the twooperand integer multiply/divide operations, and the program counter (PC).
3.4
Pipeline
For integer operations, loads, stores, and other non-floating-point operations, the RM5261 implements a 5-stage integer pipeline. In addition to the integer pipeline, the RM5261 implements an extended 7-stage pipeline for floating-point operations. The RM5261 multiplies the input SysClock by 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, or 9 to produce the pipeline clock. Figure 3 shows the RM5261 integer pipeline. As illustrated in the figure, up to five integer instructions can be executing simultaneously.
Figure 3 Pipeline
I0 I1 I2 I3 I4
1I
2I
1R 1I
2R 2I
1A 1R 1I
2A 2R 2I
1D 1A 1R 1I
2D 2A 2R 2I
1W 1D 1A 1R 1I
2W 2D 2A 2R 2I 1W 1D 1A 1R 2W 2D 2A 2R 1W 1D 1A 2W 2D 2A 1W 1D 2W 2D 1W 2W
one cycle 1I-1R: Instruction cache access 2I: Instruction virtual to physical address translation 2R: Register file read, Bypass calculation, Instruction decode, Branch address calculation 1A: Issue or slip decision, Branch decision 1A: Data virtual address calculation 1A-2A: Integer add, logical, shift 2A: Store Align 2A-2D: Data cache access and load align 1D: Data virtual to physical address translation 2W: Register file write
3.5
Register File
The RM5261 has thirty-two general purpose registers with register location 0 (r0) hard-wired to a zero value. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.
3.6
ALU
The RM5261 ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder performs address calculations in addition to arithmetic operations. The logic unit performs all logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle.
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3.7
Integer Multiply/Divide
The RM5261 has a dedicated integer multiply/divide unit optimized for high-speed multiply and multiply-accumulate operations. Table 1 shows the performance of the multiply/divide unit on each operation.
Table 1 Integer Multiply/Divide Operations Opcode
MULT/U, MAD/U MUL DMULT, DMULTU DIV, DIVD DDIV, DDIVU
Operand Size
16 bit 32 bit 16 bit 32 bit any any any
Repeat Latency Rate
3 4 3 4 7 36 68 2 3 2 3 6 36 68
Stall Cycles
0 0 1 2 0 0 0
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in the Hi and Lo registers. These values can then be transferred to the general purpose register file using the Move-from-Hi and Move-from-Lo (MFHI/MFLO) instructions. In addition to the baseline MIPS IV integer multiply instructions, the RM5261 also implements the 3-operand multiply instruction, MUL. This instruction specifies that the multiply result go directly to the integer register file rather than the Lo register. The portion of the multiply that would have normally gone into the Hi register is discarded. For applications where it is known that the upper half of the multiply result is not required, using the MUL instruction eliminates the necessity of executing an explicit MFLO instruction. Also included in the RM5261 are the multiply-add instructions, MADU/MAD. This instruction multiplies two operands and adds the resulting product to the current contents of the Hi and Lo registers. The multiply-accumulate operation is the core primitive of almost all signal processing algorithms allowing the RM5261 to eliminate the need for a separate DSP engine in many embedded applications.
3.8
Floating-Point Co-Processor
The RM5261 incorporates a high-performance fully pipelined floating-point co-processor which includes a floating-point register file and autonomous execution units for multiply/add/convert and divide/square root. The floating-point coprocessor is a tightly coupled execution unit, decoding and executing instructions in parallel with, and in the case of floating-point loads and stores, in cooperation with the integer unit. The superscalar capabilities of the RM5261 allow floating-point computation instructions to issue concurrently with integer instructions.
3.9
Floating-Point Unit
The RM5261 floating-point execution unit supports single and double precision arithmetic, as specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root
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unit and a pipelined multiply/add unit. Overlap of the divide/square root and multiply/add operations is supported. The RM5261 maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. Precise exceptions are extremely important in object-oriented programming environments and highly desirable for debugging in any environment. Floating-point operations include: * * * * * * * * * * * add subtract multiply divide square root reciprocal reciprocal square root conditional moves conversion between fixed-point and floating-point format conversion between floating-point formats floating-point compare.
Table 2 gives the latencies of the floating-point instructions in internal processor cycles.
Table 2 Floating-Point Instruction Cycles Operation
fadd fsub fmult fmadd fmsub fdiv fsqrt frecip frsqrt fcvt.s.d fcvt.s.w fcvt.s.l fcvt.d.s fcvt.d.w fcvt.d.l fcvt.w.s fcvt.w.d fcvt.l.s
Latency
4 4 4/5 4/5 4/5 21/36 21/36 21/36 38/68 4 6 6 4 4 4 4 4 4
Repeat Rate
1 1 1/2 1/2 1/2 19/34 19/34 19/34 36/66 1 3 3 1 1 1 1 1 1
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Operation
fcvt.l.d fcmp fmov fmovc fabs fneg
Latency
4 1 1 1 1 1
Repeat Rate
1 1 1 1 1 1
Note:
Numbers are represented as single/double precision format.
3.10 Floating-Point General Register File
The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the floating-point load and store double instructions (LDC1 and SDC1) the floating-point unit can take advantage of the 64-bit wide data cache and issue a floating-point co-processor load or store doubleword instruction in every cycle. The floating-point control register space contains two registers; one for determining configuration and revision information for the coprocessor and one for control and status information. These are primarily used for diagnostic software, exception handling, state saving and restoring, and control of rounding modes. To support superscalar operation, the FGR has four read ports and two write ports, and is fully bypassed to minimize operation latency in the pipeline. Three of the read ports and one write port are used to support the combined multiply-add instruction while the fourth read and second write port allows a concurrent floating-point load or store.
3.11 System Control Co-processor (CP0)
The system control coprocessor, also called coprocessor 0 or CP0 in the MIPS architecture, is responsible for the virtual memory sub-system, the exception control system, and the diagnostics capability of the processor. In the MIPS architecture, the system control co-processor (and thus the kernel software) is implementation dependent. The memory management unit controls the virtual memory system page mapping. It consists of an instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint instruction and data address translation buffer, JTLB, and co-processor registers used by the virtual memory mapping sub-system.
3.12 System Control Co-Processor Registers
The RM5261 incorporates all system control co-processor (CP0) registers on-chip. These registers provide the path through which the virtual memory system's page mapping is examined and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). In addition, the RM5261 includes registers to implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data error detection. Figure 4 shows the CP0 registers.
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Figure 4
CP0 Registers
PageMask 5* EntryHi 10* 47 EntryLo0 2* EntryLo1 3* Context 4* Count 9* Status 12* Index 0* TLB Random 1* Wired 6* (entries protected from TLBWR) 0 LLAddr 17* TagLo 28* TagHi 29* PRId 15* Config 16* ECC 26* XContext 20* CacheErr 27* ErrorEPC 30* EPC 14* BadVAddr 8* Compare 11* Cause 13*
* Register number
Used for memory management
Used for exception processing
3.13 Virtual to Physical Address Mapping
The RM5261 provides three modes of virtual addressing: * * * user mode kernel mode supervisor mode
This mechanism is available to system software to provide a secure environment for user processes. Bits in the CP0 register Status determine which virtual addressing mode is used. In the user mode, the RM5261 provides a single, uniform virtual address space of 1TB (2 GB in 32-bit mode). When operating in the kernel mode, four distinct virtual address spaces, totalling over 2.5TB (4 GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address. The RM5261 processors also support a supervisor mode in which the virtual address space over 2TB (2.5 GB in 32-bit mode), divided into three regions based on the high-order bits of the virtual address. When the RM5261 is configured as a 64-bit microprocessor, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout. Figure 5 shows the address space layout for 32-bit operation.
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Figure 5 Kernel Mode Virtual Addressing (32-bit)
0xFFFFFFFF Kernel virtual address space (kseg3) 0xE0000000 Mapped, 0.5GB 0xDFFFFFFF Supervisor virtual address space (ksseg) 0xC0000000 Mapped, 0.5GB 0xBFFFFFFF Uncached kernel physical address space (kseg1) 0xA0000000 Unmapped, 0.5GB 0x9FFFFFFF Cached kernel physical address space (kseg0) 0x80000000 Unmapped, 0.5GB 0x7FFFFFFF User virtual address space (kuseg) Mapped, 2.0GB
0x00000000
3.14 Joint TLB
For fast virtual-to-physical address translation, the RM5261 uses a large, fully associative TLB that maps 96 virtual pages to their corresponding physical addresses. As indicated by its name, the joint TLB (JTLB) is used for both instruction and data translations. The JTLB is organized as 48 pairs of even-odd entries, and maps a virtual address and address space identifier into the large, 64 GB physical address space. Two mechanisms are provided to assist in controlling the amount of mapped space and the replacement characteristics of various memory regions. First, the page size can be configured, on a per-entry basis, to use page sizes in the range of 4 KB to 16 MB (in multiples of 4). The CP0 Page Mask register is loaded with the desired page size of a mapping, and that size is stored into the TLB along with the virtual address when a new entry is written. Thus, operating systems can create special purpose maps; for example, an entire frame buffer can be memory mapped using only one TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The RM5261 provides a random replacement algorithm to select a TLB entry to be written with a new mapping; however, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism allows the operating system to guarantee that certain pages are always mapped for performance
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reasons and for deadlock avoidance. This mechanism also facilitates the design of real-time systems by allowing deterministic access to critical software. The JTLB also contains information that controls the cache coherency protocol for each page. Specifically, each page has attribute bits to determine whether the coherency algorithm is one of the following: * * * * * * * uncached non-coherent write-back non-coherent write-through with write-allocate non-coherent write-through without write-allocate sharable exclusive update.
The non-coherent protocols are used for both code and data on the RM5261, with data using writeback or write-through depending on the application. The coherency attributes generate coherent transaction types on the system interface. However, in the RM5261 cache coherency is not supported. Hence the coherency attributes should never be used.
3.15 Instruction TLB
The RM5261 implements a 2-entry instruction TLB (ITLB) to minimize contention for the JTLB, eliminate the timing critical path of translating through a large associative array, and save power. Each ITLB entry maps a 4 KB page. The ITLB improves performance by allowing instruction address translation to occur in parallel with data address translation. When a miss occurs on an instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the JTLB. The operation of the ITLB is completely transparent to the user.
3.16 Data TLB
The RM5261 implements a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB. Each DTLB entry maps a 4 KB page. The DTLB improves performance by allowing data address translation to occur in parallel with instruction address translation. When a miss occurs on a data address translation by the DTLB, the DTLB is filled from the JTLB. The DTLB refill is pseudo-LRU: the least recently used entry of the least recently used pair of entries is filled. The operation of the DTLB is completely transparent to the user.
3.17 Cache Memory
The RM5261 incorporates on-chip instruction and data caches that can be accessed in a single processor cycle. Each cache has its own 64-bit data path and both caches can be accessed simultaneously. The cache subsystem provides the integer and floating-point units with an aggregate bandwidth of 3.2 GB per second at an internal clock frequency of 200 MHz.
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3.18 Instruction Cache
The RM5261 incorporates a two-way set associative on-chip instruction cache. This virtually indexed, physically tagged cache is 32 KB in size and is protected with word parity. Since the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, further increasing performance by allowing these two operations to occur simultaneously. The cache tag contains a 24-bit physical address, a valid bit, and a single parity bit. The instruction cache is 64-bits wide and can be accessed each processor cycle. Accessing 64 bits per cycle allows the instruction cache to supply two instructions per cycle to the superscalar dispatch unit. For typical code sequences where a floating-point load or store and a floating-point computation instruction are being issued together in a loop, the entire bandwidth available from the instruction cache will be consumed. Cache miss refill writes 64 bits per cycle to minimize the cache miss penalty. The line size is eight instructions (32 bytes) to maximize the performance of communication between the processor and the memory system. Like the R4650, the RM5261 supports cache locking. The contents of one set of the cache, set A, can be locked by setting a bit in the coprocessor 0 Status register. Locking the set prevents its contents from being overwritten by a subsequent cache miss. Refill will occur only into set B. This mechanism allows the programmer to lock critical code into the cache thereby guaranteeing deterministic behavior for the locked code sequence.
3.19 Data Cache
For fast, single cycle data access, the RM5261 includes a 32 KB on-chip data cache that is twoway set associative with a fixed 32-byte (eight words) line size. The data cache is protected with byte parity and its tag is protected with a single parity bit. It is virtually indexed and physically tagged to allow simultaneous address translation and data cache access. Cache protocols supported for the data cache are: 1. Uncached Data loads and instruction fetches from uncached memory space are brought in from the main memory to the register file and the execution unit, respectfully. The caches are not accessed. Data stores to uncached memory space go directly to the main memory without updating the data cache. 2. Write-back Loads and instruction fetches first search the cache, reading main memory only if the desired data is not cache resident. On data store operations, the cache is first searched to determine if the target address is cache resident. If it is resident, the cache contents are updated, and the cache line is marked for later write-back. If the cache lookup misses, the target cache line is first brought into the cache and then the write is performed as above.
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3. Write-through with write allocate Loads and instruction fetches first search the cache, reading main memory only if the desired data is not cache resident. On data store operations, the cache is first searched to determine if the target address is cache resident. If it is resident, the cache contents are updated and main memory is written, leaving the write-back bit of the cache line unchanged. If the cache lookup misses, the target line is first brought into the cache and then the write is performed as above. 4. Write-through without write allocate Loads and instruction fetches first search the cache, reading main memory only if the desired data is not cache resident. On data store operations, the cache is first searched to determine if the target address is cache resident. If it is resident, the cache contents are updated and main memory is written, leaving the write-back bit of the cache line unchanged. If the cache lookup misses, then only main memory is written. The most commonly used write policy is write-back, where a store to a cache line does not immediately cause the main memory to be updated. This increases system performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. Software can, however, select write-through on a per-page basis when appropriate, such as for frame buffers. Associated with the data cache is the store buffer. When the RM5261 executes a store instruction, this single-entry buffer gets written with the store data while the tag comparison is performed. If the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). The store buffer allows the RM5261 to execute a store every processor cycle and to perform back-to-back stores without penalty. In the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred. The RM5261 cache attributes for both the instruction and data caches are summarized in Table 3.
Table 3 Cache Attributes Characteristics
Size Organization Line size Index Tag Write policy Read order Write order miss restart after transfer of Parity Cache locking
Instruction
32KB 2-way set associative 32B vAddr11..0 pAddr31..12 n.a. sub-block sequential entire line per-word set A
Data
32KB 2-way set associative 32B vAddr11..0 pAddr31..12 write-back/write-through sub-block sequential first double per-byte set A
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3.20 Write buffer
Writes to external memory, whether cache miss write-backs or stores to uncached or write-through addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in parallel with the memory update. For uncached and write-through stores, the write buffer significantly increases performance by decoupling the SysAD bus transfers from the instruction execution stream.
3.21 System Interface
The system interface consists of a 64-bit Address/Data bus with 8 parity check bits and a 9-bit command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is capable of transferring data between the processor and memory at a peak rate of 800 MB/sec with a 100 MHz SysClock. Figure 6 shows a typical embedded system using the RM5261. In this example, a bank of DRAMs and a memory controller ASIC share the processor's SysAD bus while the memory controller provides separate ports to a boot ROM and an I/O system.
Figure 6 Typical Embedded System Block Diagram
Control DRAM Address Flash/ Boot Rom
8
72
x
x
Latch
RM5261
72 23
Memory I/O Controller
PCI Bus
3.22 System Address/Data Bus
The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RM5261 and the rest of the system. It is protected with an 8-bit parity check bus (SysADC). The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies. The Block Write data rate, Non-block Write protocol, and Output Drive Strength are programmable at Boot time via the Mode Control bits. The rate at which the processor receives data is fully controlled by the external device.
3.23 System Command Bus
The RM5261 interface has a 9-bit System Command (SysCmd) bus. The command bus indicates whether the SysAD bus carries address or data information on a per-clock basis. If the SysAD
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carries address, the SysCmd bus indicates what type of transaction is to take place (for example, a read or write). If the SysAD carries data, the SysCmd bus provides information about the data (for example, this is the last data word transmitted, or the data contains an error). The SysCmd bus is bidirectional to support both processor requests and external requests to the RM5261. Processor requests are initiated by the RM5261 and responded to by an external device. External requests are issued by an external device and require the RM5261 to respond. The RM5261 supports one- to eight-byte transfers as well as block transfers on the SysAD bus. In the case of a sub-double word transfer, the three low-order address bits give the byte address of the transfer, and the SysCmd bus indicates the number of bytes being transferred.
3.24 Handshake Signals
There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an external device to indicate to the RM5261 whether it can accept a new read or write transaction. The RM5261 samples these signals before deasserting the address on read and write requests. ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the processor to an external device. When an external device needs to control the interface, it asserts ExtRqst*. The RM5261 responds by asserting Release* to release the system interface to slave state. ValidOut* and ValidIn* are used by the RM5261 and the external device respectively to indicate that there is a valid address, command or data on the SysAD and SysCmd buses. The RM5261 asserts ValidOut* when it is driving these buses with a valid address, a command or data, and the external device drives ValidIn* when it has control of the system interface and is driving a valid address, command or data.
3.25 Non-overlapping System Interface
The RM5261 requires a non-overlapping system interface, compatible with the R5000. This means that only one processor request may be outstanding at a time and that the request must be serviced by an external device before the RM5261 issues another request. The RM5261 can issue read and write requests to an external device, whereas an external device can issue null and write requests to the RM5261. For processor reads the RM5261 asserts ValidOut* and simultaneously drives the address and read command on the SysAD and SysCmd buses respectively. If the system interface has RdRdy* asserted, then the processor tristates its drivers and releases the system interface to the slave state by asserting Release*. The external device can then begin sending data to the RM5261. Figure 7 shows a processor block read request and the external agent read response. The read latency is four cycles (ValidOut* to ValidIn*), and the response data pattern is DDDD, indicating that data can be transferred on every clock with no wait states in-between.
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Figure 7
SysClock
Processor Block Read
SysAD SysCmd ValidOut* ValidIn*
Addr Read
Data0 NData
Data1 NData
Data2 NData
Data3 NEOD
RdRdy* WrRdy*
Release*
Figure 8 shows a processor block write using write response pattern DDDD, or code 0, of the boottime mode select options.
Figure 8 Processor Block Write
SysClock
SysAD SysCmd
Addr Write
Data0 NData
Data1 NData
Data2 NData
Data3 NEOD
ValidOut* ValidIn*
RdRdy* WrRdy*
Release*
3.26 Enhanced Write Modes
The RM5231 implements two enhancements to the original R4000 write mechanism: Write Reissue and Pipeline Writes. The original R4000 allowed a write address cycle on the SysAD bus only once every four SysClock cycles. Hence for a non-block write, this meant that two out of every four cycles were wait states. Pipelined write mode eliminates these two wait states by allowing the processor to drive a new write address onto the bus immediately after the previous data cycle. This allows for higher SysAD bus utilization. However, at high bus frequencies the processor may drive a subsequent write onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not accept another write cycle. This can cause the write cycle to be missed. Write reissue mode is an enhancement to pipelined write mode and allows the processor to reissue missed write cycles. If WrRdy* is deasserted during the issue phase of a write operation, the cycle is aborted by the processor and reissued at a later time.
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In write reissue mode, a write rate of one write every two bus cycles can be achieved. Pipelined writes have the same two bus cycle write repeat rate, but can issue one additional write following the deassertion of WrRdy*.
3.27 External Requests
The External Request pin, ExtRqst*, is asserted by the external agent when it requires mastership of the system interface, either to perform an independent transfer or to write to the interrupt register within the RM5261. An independent transfer is a data transfer between two external agents or between an external agent and the memory or peripheral on the system interface. Following the assertion of ExtRqst*, the RM5261 tri-states its drivers allowing the external agent to use the system interface buses to complete an independent transfer. The external agent is responsible for returning mastership of the system interface to the RM5231 when it has completed the independent transfer and does so by executing an External Null cycle.
3.28 Interrupt Handling
The RM5261 supports a dedicated interrupt vector. When enabled by the real time executive (by setting a bit in the Cause register), interrupts vector to a specific address that is not shared with any of the other exception types. This capability eliminates the need to go through the normal software routine for exception decode and dispatch, thereby lowering interrupt latency.
3.29 Standby Mode
The RM5261 provides a means to reduce the amount of power consumed by the internal core when the CPU would otherwise not be performing any useful operations. This state is known as Standby Mode. Executing the WAIT instruction enables interrupts and causes the processor to enter Standby Mode. When the wait instruction completes the W pipe stage, and if the SysAD bus is currently idle, the internal processor clock stops, thereby freezing the pipeline. The phase lock loop, or PLL, internal timer/counter, and the "wake up" input pins: Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset* will continue to operate in their normal fashion. If the SysAD bus is not idle when the WAIT instruction completes the W pipe-stage, then the WAIT is treated as a NOP until the bus operation is completed. Once the processor is in Standby, any interrupt, including the internally generated timer interrupt, causes the processor to exit Standby mode and resume operation where it left off. The WAIT instruction is typically inserted in the idle loop of the operating system or real time executive.
3.30 JTAG Interface
The RM5261 interface supports JTAG Test Access Port (TAP) boundary scan in conformance with the IEEE 1149.1 specification. The JTAG interface is especially helpful for checking the integrity of the processors pin connections.
3.31 Boot-Time Options
Fundamental operational modes for the processor are initialized by the boot-time mode control interface. This serial interface operates at a very low frequency (SysClock divided by 256). The low frequency operation allows the initialization information to be kept in a low cost EPROM or system interface ASIC.
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Immediately after the VccOK signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all the fundamental operational modes. ModeClock run continuously from the assertion of VccOK.
3.32 Boot-Time Modes
The boot-time serial mode stream is defined in Table 4. Bit 0 is the bit presented to the processor as the first bit in the stream when VccOK is asserted. Bit 255 is the last bit transferred.
Table 4 Boot-Time Mode Bit Stream Mode bit
0
Description
reserved (must be zero)
Mode bit
14:13
Description
Output driver strength - 100% = fastest
00: 67% strength 01: 50% strength 10: 100% strength 11: 83% strength
4:1
Write-back data rate
0: DDDD 1: DDxDDx 2: DDxxDDxx 3: DxDxDxDx 4: DDxxxDDxxx 5: DDxxxxDDxxxx 6: DxxDxxDxxDxx 7: DDxxxxxxDDxxxxxx 8: DxxxDxxxDxxxDxxx 9-15 reserved
15
Reserved: Must be zero
7:5
Pclock to SysClock Multiplier
Mode Bits 7:5 Mode Bit 20=0 Mode Bit 20=1 000 Multiply by 2 n/a 001 Multiply by 3 n/a 010 Multiply by 4 n/a 011 Multiply by 5 Multiply by 2.5 100 Multiply by 6 n/a 101 Multiply by 7 Multiply by 3.5 110 Multiply by 8 n/a 111 Multiply by 9 Multiply by 4.5
17:16
System configuration identifiers - software visible in Config[21..20] register
8
Specifies byte ordering. Logically ORed with BigEndian input signal.
0: Little endian 1: Big endian
19:18
Reserved: Must be zero
10:9
Non-Block Write Protocol
00: R4000 compatible 01: reserved 10: pipelined 11: write re-issue
20
Select Pclock to SysClock Multiply Mode
0: Integer Multipliers 1: Half-Integer Multipliers
11
Timer Interrupt Enable/Disable
0: Enable the timer interrupt on Int5* 1: Disable the timer interrupt on Int5*
21
External Bus Width
0: 64-bit 1: 32-bit
12
Reserved: Must be zero
255:22
Reserved: Must be zero
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4
Pin Descriptions
The following is a list of interface, interrupt, and miscellaneous pins available on the RM5261.
Table 5 System Interface Pin Name
ExtRqst* Release*
Type
Input Output
Description
External Request Signals that the system interface is submitting an external request. Release interface Signals that the processor is releasing the system interface to slave state. Read Ready Signals that an external agent can now accept a processor read. Write Ready Signals that an external agent can now accept a processor write request. Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. Valid Output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. System Address/Data bus A 64-bit address and data bus for communication between the processor and an external agent. System Address/Data check bus An 8-bit bus containing parity check bits for the SysAD bus during data cycles. System Command/Data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. Reserved for system command/data identifier bus parity For the RM5261, unused on input and zero on output.
RdRdy* WrRdy*
Input Input
ValidIn*
Input
ValidOut*
Output
SysAD[63:0]
Input/Output
SysADC[7:0]
Input/Output
SysCmd[8:0]
Input/Output
SysCmdP
Input/Output
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Table 6 Clock/Control Interface Pin Name
SysClock
Type
Input
Description
System Clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization Quiet Vcc for PLL Quiet Vcc for the internal phase locked loop. Must be connected to VccInt through a filter circuit. Quiet Vss for PLL Quiet Vss for the internal phase locked loop. Must be connected to Vss through a filter circuit.
VccP
Input
VssP
Input
Table 7 Interrupt Interface Pin Name
Int[5:0]*
Type
Input
Description
Interrupt Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. Non-maskable interrupt Non-maskable interrupt, ORed with bit 6 of the interrupt register.
NMI*
Input
Table 8 JTAG Interface Pin Name
JTDI JTCK JTDO JTMS
Type
Input Input Output Input
Description
JTAG data in JTAG serial data in. JTAG clock input JTAG serial clock input. JTAG data out JTAG serial data out. JTAG command JTAG command signal, signals that the incoming serial data is command data.
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Table 9 Initialization Interface Pin Name
BigEndian VccOK
Type
Input Input
Description
Allows the system to change the processor addressing mode without rewriting the mode ROM. Vcc is OK When asserted, this signal indicates to the RM5261 that the 3.3V power supply has been above 3.0V for more than 100 milliseconds and will remain stable. The assertion of VccOK initiates the reading of the boot-time mode control serial stream. Cold reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with SysClock. Reset This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with SysClock. Boot mode clock Serial boot-mode data clock output at the system clock frequency divided by 256. Boot mode data in Serial boot-mode data input.
ColdReset*
Input
Reset*
Input
ModeClock
Output
ModeIn
Input
Table 10 Power Supply
Pin Name VccInt VccIO Vss Note 1. An "*" at the end of the signal denotes active low. Input Input Input Type Power supply for core. Power supply for I/O. Ground return. Description
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5
Absolute Maximum Ratings1
Symbol
VTERM TCASE
Rating
Terminal Voltage with respect to Vss Operating Temperature Commercial Industrial
Limits
-0.52 to +3.9
Unit
V
0 to +85 -45 to +85 -55 to +125 203 204
C C C mA mA
TSTG IIN IOUT Notes 1.
Storage Temperature DC Input Current DC Output Current
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VIN minimum = -2.0 V for pulse width less than 15 ns. VIN should not exceed 3.9 Volts. When VIN < 0V or VIN > VccIO Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds.
2. 3. 4.
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6
Recommended Operating conditions
Grade
Commercial Industrial Notes 1. 2. 3. 4. VccIO should not exceed VccInt by greater than 1.2V during the power-up sequence. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended. As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. VccP must be connected to VccInt through a passive filter circuit. See the RM5200 User's Manual for the recommended filter circuit.
Temperature
0C to +85C (Case) -40C to +85C (Case)
Vss
0V 0V
VccInt
2.5 V 5% 2.5 V 5%
VccIO
VccP
3.15 V to 3.45 V 2.5 V 5% 3.15 V to 3.45 V 2.5 V 5%
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7
DC Electrical Characteristics
Table 11 DC Electrical Characteristics
Parameter VOL VOH VOL VOH VIL VIH IIN 2.4V -0.3V 2.0V 0.8V VccIO + 0.3V 15 A 15 A VIN = 0 VIN = VccIO VccIO - 0.2V 0.4V |IOUT| = 2 mA
Minimum
Maximum
0.2V
Conditions
|IOUT|= 100 A
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8
Power Consumption
Conditions: Max: VccInt = 2.625 Parameter
VccInt standby Power active (mWatts)
CPU Clock Speed 200 MHz Typ1
1600 1750
250 MHz Typ1
1850 2025
266 MHz Typ1
1900 2075
Typ: VccInt = 2.5V
No SysAD bus activity R4000 write protocol with no FPU operation Write re-issue or pipelined writes with superscalar
Max2
350 3200 3500
Max2
435 3700 4050
Max2
450 3800 4150
Notes 1. 2. 3. Typical integer instruction mix with nominal supply voltage (untested). Worst case instruction mix with maximum supply voltage. I/O supply power is application dependent, but typically <20% of VccInt.
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9
9.1
AC Electrical Characteristics
Capacitive Load Deration
Parameter
Load Derate IO Power Derate IO Power Derate @ 20pF load 4.0
Symbol
CLD
Min
Max
2 21 5.5
Units
ns/25pF mW/25pF/MHz mW/MHz
9.2
Clock Parameters
CPU Speed Test Parameter
SysClock High SysClock Low SysClock Frequency1 SysClock Period Clock Jitter for SysClock SysClock Rise Time SysClock Fall Time ModeClock Period JTAG Clock Period Note 1. Operation of the RM5261 is only guaranteed with the Phase Lock Loop Enabled. tSCP tJI tCR tCF tModeCKP tJTAGCKP 4
200 MHz Min
3 3 25 100 40 200 2 2 256
250 MHz
3 3 25 125 40 150 2 2 256 4
266 MHz Max Units
ns ns 106 30 150 2 2 256 4 MHz ns ps ns ns tSCP tSCP 3 3 33.3
Symbol
tSCH tSCL
Conditions
Transition 5ns Transition 5ns
Max Min
Max Min
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9.3
System Interface Parameters1
200-266 MHz Parameter
Data Output2,3
Symbol
tDO
Conditions
mode14:13 = 105 (fastest) mode14:13 = 115 mode14:13 = 005 mode14:13 = 015 (slowest)
Min
1.0 1.0 1.0 1.0 2.5 1.0
Max
4.5 5.0 5.5 6.0
Units
ns ns ns ns ns ns
Data Setup4 Data Hold4 Notes 1. 2. 3. 4. 5.
tDS tDH
trise = see above table tfall = see above table
Timings are measured from 1.5 V of the clock to 1.5 V of the signal. Capacitive load for all maximum output timings is 50 pF. Minimum output timings are for a theoretical no load condition - untested. Data Output timing applies to all signal pins whether tristate I/O or output only. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only. Only mode 14:13 = 00 is tested and guaranteed.
9.4
Boot-Time Interface Parameters
Parameter
Mode Data Setup Mode Data Hold
Symbol
tDS(M) tDH(M)
Min
4 0
Max
Units
SysClock cycles SysClock cycles
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10
Timing Diagrams
Figure 9 Clock Timing
SysClock tRise tFall tHigh tLow tJitterIn
10.1 System Interface Timing
(SysAD, SysCmd, ValidIn*, ValidOut*, etc.)
Figure 10 Input Timing
SysClock tDS Data Data tDH
Figure 11 Output Timing
SysClock tDOmax Data tDOmin Data Data
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11
Packaging Information
10
208
D4 D3
5 D1 2.00 DIA 4 PLACES DA-B H 0.20 E/2 D3 4X D1/2
7 ODD LEAD SIDES
D/2 A3
(D2) (b)
SEE DETAIL "A"
1
E3 Pin #1 I.D. 11.0 REF.
(E2) E4 7 5 E1 E1/2 11.0 REF.
X3 X = A, B, OR D EVEN LEAD SIDES e/2
4X
0.20 C A-BD 11.0 REF.
B3 4.00 R. 4 PLACES
"COUNTRY OF ORIGIN" MARK 3.00 REF. DIA. 4 PLACES BOTTOM VIEW
11.0 REF. X3 X = A, B, OR D DETAIL "A"
TOP VIEW SEATING PLANE C 8 12-16 SEE DETAIL "B" A
0.40 MIN. 0 MIN.
(N-4)X e b 11 b WITH LEAD FINISH 0.13/0.19 b1 11 BASE METAL SECTION C-C 11 A1 13 DETAIL "B" 2H 0.10 A2 0.13 R. MIN. C
aaa M C A-B D 8
0.076 C
0.13/0.30 R
GAGE PLANE 0.25
11 0.13/0.23
C L 1.30 REF.
0-7
All dimensions are in millimeters unless otherwise noted.
208PQ4 Symbol A A1 A2 D D1 Min Nominal -3.70 Max 4.07 -3.60 To be determined at seating Plane C. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 MM per side. Dimension D1 and E1 do include mold mismatch and are determined at Datum Plane H. Note
0.25 0.33 3.20 3.37 30.60 BSC 28.00 BSC
D2 E E1
25.00 REF. 30.60 BSC 28.00 BSC To be determined at seating Plane C. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 MM per side. Dimension D1 and E1 do include mold mismatch and are determined at Datum Plane H.
E2 D3 E3 L e b b1
25.00 REF. 21.0 REF. 21.0 REF. 0.46 0.56 0.50 BSC 0.17 0.22 0.17 0.20 0.27 0.23 0.66
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208PQ4 Symbol aaa ThetaJa ThetaJc Min Nominal 0.08 13.7 C/W 1.5 C/W Max Note
Notes 1. 2. 3. 4. 5. 6. 7. 8. All dimensioning and tolerances confirm to ASME Y14.5-1994. Datum Plane H located at the bottom of the mold parting line and coincident with where lead exits plastic body. Datums A-B and D to be determined where center line between leads exits plastic body at Datum Plane H. To be determined at seating Plane C. Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.254 MM per side. Dimension D1 and E1 do include mold mismatch and are determined at Datum Plane H. "N" is number of terminals. Package top dimensions are smaller than bottom dimensions by 0.20 millimeters and top of package will not overhang bottom of package. Dimensions b does not include Damabr protrusion. Allowable Damabr protrusion shall be 0.08 MM. Total in excess of b dimension at maximum material condition. Damabr can not be located on the lower radius or the foot. The dimension space between protrusion and an adjacent lead shall not be less than 0.07 MM for 0.4 MM and 0.50 MM pitch package. All dimensions are in millimeters.
9.
10. The optional exposed heat shrink is coincident with the top or bottom side of the package and not allowed to protrude beyond that surface. 11. These dimensions apply to the flat section of the lead between 0.10 MM and 0.25 MM from the lead tip. 12. This drawing conforms to JEDEC registered outline MS-029. But the heat slug dimension was not specified on JEDEC. 13. A1 is defined as the distance from the seating plane to the lowest point of the package body.
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12
RM5261 208-pin PQFP Package Pinout
Pin
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97 101 105 109 113 117 121 125 129 133 137 141 145 149
Function
VccIO Vss SysAD37 SysAD38 SysAD39 Vss Vss SysAD43 SysAD44 SysAD45 Vss Vss JTCK NC Vss ValidIn* VssP VccIO SysCmd0 VccIO VccIO SysCmd8 VccInt Int0* Int4* NC VccIO ColdReset* Vss Vss SysAD50 SysAD51 SysAD52 Vss Vss SysAD56 SysAD57 SysAD58
Pin
2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150
Function
NC SysAD4 VccInt VccIO SysAD8 SysAD9 SysAD10 VccInt VccIO SysAD14 SysAD15 ModeClock JTMS NC ModeIn ValidOut* SysClock Vss SysCmd1 Vss Vss SysCmdP Vss Int1* Int5* NC NMI* VccOK SysAD16 SysAD17 VccIO VccInt SysAD21 SysAD22 SysAD23 VccIO VccInt SysAD27
Pin
3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 67 71 75 79 83 87 91 95 99 103 107 111 115 119 123 127 131 135 139 143 147 151
Function
NC SysAD36 Vss Vss SysAD40 SysAD41 SysAD42 Vss Vss SysAD46 SysAD47 JTDO VccIO NC RdRdy* Release* VccInt VccInt SysCmd2 SysCmd4 SysCmd6 VccInt VccIO Int2* VccIO NC ExtRqst* BigEndian SysAD48 SysAD49 Vss Vss SysAD53 SysAD54 SysAD55 Vss Vss SysAD59
Pin
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 132 136 140 144 148 152
Function
VccIO SysAD5 SysAD6 SysAD7 VccInt VccIO SysAD11 SysAD12 SysAD13 VccInt VccIO JTDI Vss VccIO WrRdy* VccP Vss Vss SysCmd3 SysCmd5 SysCmd7 Vss Vss Int3* Vss NC Reset* VccIO VccInt SysAD18 SysAD19 SysAD20 VccIO VccInt SysAD24 SysAD25 SysAD26 VccIO 38
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use Document ID: PMC-2002241, Issue 1
RM5261TM Microprocessor with 64-Bit System Bus Data Sheet Released
Pin
153 157 161 165 169 173 177 181 185 189 193 197 201 205
Function
Vss NC VccIO SysAD29 SysAD30 SysAD31 VccInt VccIO VccInt SysAD0 SysAD1 SysAD2 VccIO NC
Pin
154 158 162 166 170 174 178 182 186 190 194 198 202 206
Function
NC NC Vss SysAD61 SysAD62 SysAD63 Vss Vss Vss SysAD32 SysAD33 SysAD34 Vss NC
Pin
155 159 163 167 171 175 179 183 187 191 195 199 203 207
Function
NC NC SysAD28 VccInt VccIO SysADC2 SysADC3 SysADC0 SysADC1 VccIO VccInt SysAD3 NC VccIO
Pin
156 160 164 168 172 176 180 184 188 192 196 200 204 208
Function
Vss NC SysAD60 Vss Vss SysADC6 SysADC7 SysADC4 SysADC5 Vss Vss SysAD35 NC Vss
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use Document ID: PMC-2002241, Issue 1
39
RM5261TM Microprocessor with 64-Bit System Bus Data Sheet Released
13
Ordering Information
RM5261 -123 A I Temperature Grade: (blank) = commercial I = Industrial
Package Type: Q = Power Quad 4 (PQ-4)
Device Maximum Speed Device Type
Valid Combinations
RM5261-200-Q RM5261-250-Q RM5261-266-Q RM5261-200-QI (Contact Sales prior to design)
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer's Internal Use Document ID: PMC-2002241, Issue 1
40

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